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<meta name="description" content="关键词：触发器，锁存器 Latch 的含义 锁存器（Latch），是电平触发的存储单元，数据存储的动作取决于输入时钟（或者使能）信号的电平值。仅当锁存器处于使能状态时，输出才会随着数据输入发生变化。 当电平信号无效时，输出信号随输入信号变化，就像通过了缓冲器；当电平有效时，输出信号被锁存。激励信号的任何变化，都将直接引起锁存器输出状态的改变，很有可能会因为瞬态特性不稳定而产生振荡现象。 锁存器示意图如下：  触发器（flip-flop）..">
		
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				<h2>6.5 Verilog 避免 Latch</h2>				<h3><em>分类</em> <a href="../w3cnote_genre/verilog" title="Verilog 教程" >Verilog 教程</a> </h3>
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					<h3>关键词：触发器，锁存器</h3><h3>
Latch 的含义</h3>
<p>锁存器（Latch），是电平触发的存储单元，数据存储的动作取决于输入时钟（或者使能）信号的电平值。仅当锁存器处于使能状态时，输出才会随着数据输入发生变化。</p><p>
当电平信号无效时，输出信号随输入信号变化，就像通过了缓冲器；当电平有效时，输出信号被锁存。激励信号的任何变化，都将直接引起锁存器输出状态的改变，很有可能会因为瞬态特性不稳定而产生振荡现象。</p><p>
锁存器示意图如下：</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2020/09/UEro1jQtpyTQS4BI.png" width="50%"></p>
<p>触发器（flip-flop），是边沿敏感的存储单元，数据存储的动作（状态转换）由某一信号的上升沿或者下降沿进行同步的（限制存储单元状态转换在一个很短的时间内）。</p><p>
触发器示意图如下：</p>
<p><img decoding="async" src="https://www.runoob.com/wp-content/uploads/2020/09/DzkHnLYQkX67ZYBO.png" ></p>
<p>寄存器（register），在 Verilog 中用来暂时存放参与运算的数据和运算结果的变量。一个变量声明为寄存器时，它既可以被综合成触发器，也可能被综合成 Latch，甚至是 wire 型变量。但是大多数情况下我们希望它被综合成触发器，但是有时候由于代码书写问题，它会被综合成不期望的 Latch 结构。</p>

<p>Latch 的主要危害有：</p>
<ul><li>1）输入状态可能多次变化，容易产生毛刺，增加了下一级电路的不确定性；</li><li>2）在大部分 FPGA 的资源中，可能需要比触发器更多的资源去实现 Latch 结构；</li><li>3）锁存器的出现使得静态时序分析变得更加复杂。</li></ul>
<p>Latch 多用于门控时钟（clock gating）的控制，一般设计时，我们应当避免 Latch 的产生。</p>
<h3>
if 结构不完整</h3>
<p>组合逻辑中，不完整的 if - else 结构，会产生 latch。</p><p>
例如下面的模型，if 语句中缺少 else 结构，系统默认 else 的分支下寄存器 q 的值保持不变，即具有存储数据的功能，所以寄存器 q 会被综合成 latch 结构。</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">module</span> module1_latch1<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; data<span style="color: #5D478B;">,</span> <br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; en <span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> <span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp;q<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">*</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>en<span style="color: #9F79EE;">&#41;</span> q <span style="color: #5D478B;">=</span> data <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span><br />
</div></div>
<p>避免此类 latch 的方法主要有 2 种，一种是补全 if-else 结构，或者对信号赋初值。</p><p>
例如，上面模型中的always语句，可以改为以下两种形式：</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">// 补全条件分支结构 &nbsp; &nbsp;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">*</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>en<span style="color: #9F79EE;">&#41;</span> &nbsp;q <span style="color: #5D478B;">=</span> data <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> &nbsp; &nbsp; q <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//赋初值</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">*</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; q <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>en<span style="color: #9F79EE;">&#41;</span> q <span style="color: #5D478B;">=</span> data <span style="color: #5D478B;">;</span> <span style="color: #00008B; font-style: italic;">//如果en有效，改写q的值，否则q会保持为0</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
</div></div>
<p>但是在时序逻辑中，不完整的 if - else 结构，不会产生 latch，例如下面模型。</p><p>
这是因为，q 寄存器具有存储功能，且其值在时钟的边沿下才会改变，这正是触发器的特性。</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">module</span> module1_ff<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; clk <span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; data<span style="color: #5D478B;">,</span> <br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; en <span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> <span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp;q<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk<span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>en<span style="color: #9F79EE;">&#41;</span> q <span style="color: #5D478B;">&lt;=</span> data <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span><br />
</div></div>
<p>在组合逻辑中，当条件语句中有很多条赋值语句时，每个分支条件下赋值语句的不完整也是会产生 latch。</p><p>
其实对每个信号的逻辑拆分来看，这也相当于是 if-else 结构不完整，相关寄存器信号缺少在其他条件下的赋值行为。例如：</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">module</span> module1_latch11<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; data1<span style="color: #5D478B;">,</span> <br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; data2<span style="color: #5D478B;">,</span> <br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; en <span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> <span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp;q1 <span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> <span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp;q2<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">*</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>en<span style="color: #9F79EE;">&#41;</span> &nbsp; q1 <span style="color: #5D478B;">=</span> data1 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> &nbsp; &nbsp; &nbsp;q2 <span style="color: #5D478B;">=</span> data2 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span><br />
</div></div>
<p>这种情况也可以通过补充完整赋值语句或赋初值来避免 latch。例如：</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">*</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//q1 = 0; q2 = 0 ; //或在这里对 q1/q2 赋初值</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>en<span style="color: #9F79EE;">&#41;</span> &nbsp;<span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; q1 <span style="color: #5D478B;">=</span> data1 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; q2 <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; q1 <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; q2 <span style="color: #5D478B;">=</span> data2 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
</div></div>
<h3>
case 结构不完整</h3>
<p>case 语句产生 Latch 的原理几乎和 if 语句一致。在组合逻辑中，当 case 选项列表不全且没有加 default 关键字，或有多个赋值语句不完整时，也会产生 Latch。例如：
</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
<span style="color: #A52A2A; font-weight: bold;">module</span> module1_latch2<span style="color: #9F79EE;">&#40;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; data1<span style="color: #5D478B;">,</span> <br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> &nbsp; &nbsp; &nbsp; data2<span style="color: #5D478B;">,</span> <br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">input</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">1</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> sel <span style="color: #5D478B;">,</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">output</span> <span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp;q <span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">*</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">case</span><span style="color: #9F79EE;">&#40;</span>sel<span style="color: #9F79EE;">&#41;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">2'b00</span><span style="color: #5D478B;">:</span> &nbsp;q <span style="color: #5D478B;">=</span> data1 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">2'b01</span><span style="color: #5D478B;">:</span> &nbsp;q <span style="color: #5D478B;">=</span> data2 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">endcase</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
<span style="color: #A52A2A; font-weight: bold;">endmodule</span><br />
</div></div><p>
当然，消除此种 latch 的方法也是 2 种，将 case 选项列表补充完整，或对信号赋初值。</p><p>
补充完整 case 选项列表时，可以罗列所有的选项结果，也可以用 default 关键字来代替其他选项结果。</p><p>
例如，上述 always 语句有以下 2 种修改方式。</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">*</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">case</span><span style="color: #9F79EE;">&#40;</span>sel<span style="color: #9F79EE;">&#41;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">2'b00</span><span style="color: #5D478B;">:</span> &nbsp; &nbsp;q <span style="color: #5D478B;">=</span> data1 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">2'b01</span><span style="color: #5D478B;">:</span> &nbsp; &nbsp;q <span style="color: #5D478B;">=</span> data2 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">default</span><span style="color: #5D478B;">:</span> &nbsp;q <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">endcase</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">*</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">case</span><span style="color: #9F79EE;">&#40;</span>sel<span style="color: #9F79EE;">&#41;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">2'b00</span><span style="color: #5D478B;">:</span> &nbsp;q <span style="color: #5D478B;">=</span> data1 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">2'b01</span><span style="color: #5D478B;">:</span> &nbsp;q <span style="color: #5D478B;">=</span> data2 <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">2'b10</span><span style="color: #5D478B;">,</span> <span style="color: #ff0055;">2'b11</span> <span style="color: #5D478B;">:</span> &nbsp;<br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; q <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">endcase</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
</div></div>
<h3>
原信号赋值或判断</h3><p>
在组合逻辑中，如果一个信号的赋值源头有其信号本身，或者判断条件中有其信号本身的逻辑，则也会产生 latch。因为此时信号也需要具有存储功能，但是没有时钟驱动。此类问题在 if 语句、case 语句、问号表达式中都可能出现，例如：</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//signal itself as a part of condition</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">reg</span> a<span style="color: #5D478B;">,</span> b <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">*</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>a <span style="color: #5D478B;">&amp;</span> b<span style="color: #9F79EE;">&#41;</span> &nbsp;a <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span> &nbsp; <span style="color: #00008B; font-style: italic;">//a -&gt; latch</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> a <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
&nbsp; &nbsp; <br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//signal itself are the assigment source </span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; &nbsp; &nbsp; &nbsp;c<span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">wire</span> <span style="color: #9F79EE;">&#91;</span><span style="color: #ff0055;">1</span><span style="color: #5D478B;">:</span><span style="color: #ff0055;">0</span><span style="color: #9F79EE;">&#93;</span> sel <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">*</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">case</span><span style="color: #9F79EE;">&#40;</span>sel<span style="color: #9F79EE;">&#41;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">2'b00</span><span style="color: #5D478B;">:</span> &nbsp; &nbsp;c <span style="color: #5D478B;">=</span> c <span style="color: #5D478B;">;</span> &nbsp; &nbsp;<span style="color: #00008B; font-style: italic;">//c -&gt; latch</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #ff0055;">2'b01</span><span style="color: #5D478B;">:</span> &nbsp; &nbsp;c <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">default</span><span style="color: #5D478B;">:</span> &nbsp;c <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">endcase</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
<br />
&nbsp; &nbsp; <span style="color: #00008B; font-style: italic;">//signal itself as a part of condition in "? expression"</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">wire</span> &nbsp; &nbsp; &nbsp;d<span style="color: #5D478B;">,</span> sel2<span style="color: #5D478B;">;</span> <br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">assign</span> &nbsp; &nbsp;d <span style="color: #5D478B;">=</span> &nbsp;<span style="color: #9F79EE;">&#40;</span>sel2 <span style="color: #5D478B;">&amp;&amp;</span> d<span style="color: #9F79EE;">&#41;</span> <span style="color: #5D478B;">?</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">:</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span> &nbsp;<span style="color: #00008B; font-style: italic;">//d -&gt; latch</span><br />
</div></div>
<p>避免此类 Latch 的方法，就只有一种，即在组合逻辑中避免这种写法，信号不要给信号自己赋值，且不要用赋值信号本身参与判断条件逻辑。</p><p>
例如，如果不要求立刻输出，可以将信号进行一个时钟周期的延时再进行相关逻辑的组合。上述第一个产生 Latch 的代码可以描述为：</p>
<div class="example"><h2 class="example">实例</h2> <div class="example_code">
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; a<span style="color: #5D478B;">,</span> b <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">reg</span> &nbsp; a_r <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">@</span><span style="color: #A52A2A; font-weight: bold;">posedge</span> clk<span style="color: #9F79EE;">&#41;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; a_r &nbsp;<span style="color: #5D478B;">&lt;=</span> a <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">always</span> <span style="color: #5D478B;">@</span><span style="color: #9F79EE;">&#40;</span><span style="color: #5D478B;">*</span><span style="color: #9F79EE;">&#41;</span> <span style="color: #A52A2A; font-weight: bold;">begin</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">if</span> <span style="color: #9F79EE;">&#40;</span>a_r <span style="color: #5D478B;">&amp;</span> b<span style="color: #9F79EE;">&#41;</span> &nbsp;a <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b1</span> <span style="color: #5D478B;">;</span> &nbsp; <span style="color: #00008B; font-style: italic;">//there is no latch</span><br />
&nbsp; &nbsp; &nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">else</span> a <span style="color: #5D478B;">=</span> <span style="color: #ff0055;">1'b0</span> <span style="color: #5D478B;">;</span><br />
&nbsp; &nbsp; <span style="color: #A52A2A; font-weight: bold;">end</span><br />
</div></div>
<h3>
敏感信号列表不完整</h3><p>
如果组合逻辑中 always@() 块内敏感列表没有列全，该触发的时候没有触发，那么相关寄存器还是会保存之前的输出结果，因而会生成锁存器。</p><p>
这种情况，把敏感信号补全或者直接用 always@(*) 即可消除 latch。</p>

<h3>小结</h3><p>
总之，为避免 latch 的产生，在组合逻辑中，需要注意以下几点：</p>
<ul><li>
1）if-else 或 case 语句，结构一定要完整</li><li>
2）不要将赋值信号放在赋值源头，或条件判断中</li><li>
3）敏感信号列表建议多用 always@(*)</li></ul>
<h3>源码下载</h3>
<p><a href="../wp-content/uploads/2020/09/6.5latch.zip" download class="download">Download</a></p>				</div>
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	<li><a target="_top" data-id="23230" title="7.3 Verilog 串行 FIR 滤波器设计" href="../w3cnote/verilog-serial-fir.html" >7.3 Verilog 串行 FIR 滤波器设计</a></li>
	
		
	<li><a target="_top" data-id="23236" title="7.4 Verilog CIC 滤波器设计" href="../w3cnote/verilog-cic.html" >7.4 Verilog CIC 滤波器设计</a></li>
	
		
	<li><a target="_top" data-id="23260" title="7.5 Verilog FFT 设计" href="../w3cnote/verilog-fft.html" >7.5 Verilog FFT 设计</a></li>
	
		
	<li><a target="_top" data-id="23309" title="7.6 Verilog DDS 设计" href="../w3cnote/verilog-dds.html" >7.6 Verilog DDS 设计</a></li>
	
		
	<li><a target="_top" data-id="23281" title="8.1 Verilog 数值转换" href="../w3cnote/verilog-numerical-conversion.html" >8.1 Verilog 数值转换</a></li>
	
	<li><a target="_top" title="Verilog 教程高级篇" href="../w3cnote/verilog2-tutorial.html" >Verilog 教程高级篇</a></li></ul></div>	</div>
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